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ltc4222 1 4222fa typical application features applications description dual hot swap controller with i 2 c compatible monitoring the ltc ? 4222 hot swap? controller allows two power paths to be safely inserted and removed from a live back- plane. using external n-channel pass transistors, board supply voltages and inrush currents are ramped up at an adjustable rate. an i 2 c interface and onboard adc allows for monitoring of current, voltage and fault status for each channel. the device features adjustable, analog, foldback current limit circuits and a soft-start circuit that sets the di/dt of the inrush currents. an i 2 c interface may con? gure the part to latch off or automatically restart after the ltc4222 detects a fault on either channel. the controller has additional features to interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a load card and power-up either automatically upon insertion or wait for an i 2 c command to turn on. l , lt, ltc and ltm are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 7330065. advanced mezzanine card application n allows safe insertion into a live backplane n 10-bit adc monitors currents and voltages n i 2 c/smbus interface n wide operating voltage range: 2.9v to 29v n di/dt controlled soft-start n high side drive for external n-channel mosfets n no external gate capacitors required n input overvoltage/undervoltage protection n optional latchoff or auto-retry after faults n alert host after faults n inrush current limit with foldback n available in 32-pin (5mm 5mm) qfn and 36-pin ssop packages n live board insertion n electronic circuit breakers n computers, servers n platform management uv1 v dd1 sense1 C ltc4222 gate1 intv cc adr2 adr1 nc adr0 config source1 uv2 v dd2 12v 7.4a 3.3v 150ma auxpgood 12pgood sense2 C gate2 source2 ov1 ov2 alert scl sda on fb1 adin1 timer gpio1 en1 ss 10 68nf 6m si7336adp 10.2k 3.57k 10 4222 ta01a 0.1f 34k 1.02k 3.4k gnd alert scl on sda 12v adin2 fb2 gpio2 en2 0.1f 10 300m si1046r 4.99k 3.57k 10 0.1f 6.55k 1.02k 3.4k 3.3v plug-in card backplane 1f 10nf start-up waveform with sequencing v out2 10v/div v out1 10v/div gpio pgood 10v/div v in1/2 10v/div 4222 ta01b 50ms/div contact bounce
ltc4222 2 4222fa absolute maximum ratings supply voltages (v ddn ) .............................. ?0.3v to 35v supply voltage (intv cc ) ........................... ?0.3v to 6.5v input voltages gaten ? sourcen (note 3) .................... ?0.3v to 5v sense + n ..........................v ddn ? 6.5v to v ddn + 0.3v sense ? n .............................?0.3v to sense + n + 0.3v sourcen .................................................. ?5v to 35v uvn .....................................?0.3v to sense + n + 0.3v en n, fbn, on, ovn ................................ ?0.3v to 12v adr0-2, timer, ss ............... ?0.3v to intv cc + 0.3v (notes 1, 2) 32 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm s 5mm) plastic qfn 13 14 15 16 17 33 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1ss config intv cc gnd adr0 adr1 adr2 timer en1 adin1 on aler t scl sda adin2 en2 ov2 uv2 v dd2 sense2 ? gate2 source2 fb2 gpio2 ov1 uv1 v dd1 sense1 ? gate1 source1 fb1 gpio1 t jmax = 125c, ja = 34c/w exposed pad (pin 33), pcb gnd connection optional 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view g package 36-lead plastic ssop 36 25 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 sense1 ? sense1 + v dd1 uv1 ov1 ss config intv cc gnd adr0 adr1 adr2 timer ov2 uv2 v dd2 sense2 + sense2 ? gate1 source1 fb1 gpio1 en1 adin1 on1 on2 alert scl sdai sdao adin2 en2 gpio2 fb2 source2 gate2 t jmax = 125c, ja = 95c/w pin configuration order information adinn, config ...................................... ?0.3v to 12v alert , scl, sda, sdai, sdao ............ ?0.3v to 6.5v output voltages gaten, gpion ........................................ ?0.3v to 35v operating temperature range ltc4222c ................................................ 0c to 70c ltc4222i.............................................. ?40c to 85c storage temperature range ................... ?65c to 150c lead temperature (soldering, 10 sec) ssop ................................................................ 300c lead free finish tape and reel part marking* package description temperature range ltc4222cg#pbf ltc4222cg#trpbf ltc4222cg 36-lead plastic ssop 0c to 70c ltc4222ig#pbf ltc4222ig#trpbf ltc4222ig 36-lead plastic ssop ?40c to 85c ltc4222cuh#pbf ltc4222cuh#trpbf ltc4222 32-lead (5mm 5mm) plastic qfn 0c to 70c ltc4222iuh#pbf ltc4222iuh#trpbf ltc4222 32-lead (5mm 5mm) plastic qfn ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
ltc4222 3 4222fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 12v unless otherwise noted. symbol parameter conditions min typ max units supplies v ddn input supply range l 2.9 29 v i dd1 v dd1 input supply current v dd1 = 12v l 0.85 1.2 ma i dd2 v dd2 input supply current v dd2 = 12v, i intvcc = 0ma l 34ma v ddn(uvl) input supply undervoltage lockout v dd rising l 2.34 2.43 2.53 v v ddn(hyst) input supply undervoltage lockout hysteresis l 60 80 100 mv intv cc internal regulator voltage i intvcc = 0ma l 3.15 3.3 3.45 v intv cc(uvl) intv cc undervoltage lockout intv cc rising l 2.55 2.64 2.73 v intv cc(hyst) intv cc undervoltage lockout hysteresis l 35 50 65 mv current limit and circuit breaker (both channels) v sense(th) circuit breaker threshold (v dd C v sense ) l 47.5 48.75 50 50 52.5 51.25 mv mv v sense current limit voltage (v dd C v sense )v fb = 1.3v v fb = 0v start-up timer expired l l l 46 14 130 50 16.6 150 54 19 165 mv mv mv t d(oc) oc fault filter v sense = 100mv l 10 20 30 s i sense(in) sense + /sense C pin input current v sense = 12v l 02040a gate drive v gate external n-channel gate drive (v gate C v source ) (note 3) v dd = 2.9v to 29v l 4.7 5.9 6.5 v i gate(up) external n-channel gate pull-up current gate on, v gate = 0v l C8 C12 C18 a i gate(dn) external n-channel gate pull-down current gate off, v gate = 15v l 0.8 1 1.5 ma i gate(lim) pull-down current from gate to source during oc/uvlo v gate = 15v, (v dd C v sense )n = 200mv l 450 ma t phl(sense) (v dd C sense) high to gate low v dd C sense = 200mv, c gate = 10nf l 0.5 1 s v gs(powerbad) (gate-source) voltage for power bad fault v source = 2.9v to 29v l 3.8 4.3 4.7 v comparator inputs v input(th) config, en , fb, on, ov and uv input threshold v in rising l 1.215 1.235 1.255 v v config, en ,on(hyst) config, en , on hysteresis l 80 128 180 mv v fb(hyst) fb power good hysteresis l 2 7 20 mv v ov(hyst) ov hysteresis l 16 24 32 mv v uv(hyst) uv hysteresis l 60 90 110 mv i (in) config, fb, on, ov and uv input current v in = 3v l 01a i en (up) en pull-up current v en = 0v l 51020a v uv(rth) uv reset threshold voltage v uv falling l 0.36 0.4 0.46 v v uv(rhyst) uv reset threshold hysteresis l 60 125 180 mv v gpio(th) gpio input threshold v gpio rising l 0.8 1 1.2 v
ltc4222 4 4222fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 12v unless otherwise noted. symbol parameter conditions min typ max units other pin functions v gpio(ol) gpio output low voltage i gpio = 5ma l 0.25 0.4 v i gpio(oh) gpio input leakage current v gpio = 15v l 01a i source source input current source = 15v l 70 115 170 a t p(gate) input (on, ov, uv, en ) to gate off propagation delay l 35s t d(gate) gate turn-on delay on uv, ov, en overcurrent auto-retry l l l 75 4.2 4 100 5 8 125 6.7 s ms s v timerl(th) timer low threshold l 0.18 0.2 0.22 v v timerh(th) timer high threshold l 1.215 1.235 1.255 v i timer(up) timer pull-up current l 90 100 110 a i timer(down) timer pull-down current for oc auto-retry l 1.6 2.15 2.6 a i timer(up/down) timer pin oc auto-retry duty cycle l 38 50 58 n/a i ss soft-start ramp pull-up current ramping waiting for gate to slew l l 7.5 0.5 10 0.75 12.5 0.95 a a adc res resolution (no missing codes) l 10 bits v fs full-scale voltage (1023 ? v lsb )(v dd C sense) source adin l l l 64 32 1.28 mv v v lsb lsb step size (v dd C sense) source adin l l l 62.5 31.25 1.25 v mv mv v os offset error (v dd C sense) source adin l l l 3 2 2 lsb lsb lsb inl integral nonlinearity (note 5) l 0.5 lsb tue total unadjusted error/full-scale error (v dd C sense) source adin l l l 1.5 1 1 % % % r adin adin sampling resistance v adin = 1.28v l 12 m i adin adin input current v adin = 1.28v l 0 0.1 a conversion rate 15 hz
ltc4222 5 4222fa electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v dd = 12v unless otherwise noted. symbol parameter conditions min typ max units i 2 c interface v adr(h) adr0, adr1, adr2 input high voltage l intv cc C 0.8 intv cc C 0.4 intv cc C 0.2 v i adr(in,z) adr0, adr1, adr2 hi-z input current adr0, adr1, adr2 = 0.8v, intv cc C 0.8v l 5 0 C5 a v adr(l) adr0, adr1, adr2 input low voltage l 0.2 0.4 0.8 v i adr(in) adr0, adr1, adr2 input current adr0, adr1, adr2 = 0v, intv cc l C80 80 a v alert (ol) alert output low voltage i alert = 3ma l 0.2 0.4 v i alert (oh) alert input current alert = intv cc l 1 a v sda,scl(th) sda, scl input threshold l 1.5 1.7 1.9 v i sda,scl(oh) sda, scl input current scl, sda = intv cc l 1 a v sda(ol) sda output low voltage i sda = 3ma l 0.2 0.4 v i 2 c interface timing f scl(max) scl clock frequency operates with f scl f scl(max) 400 1000 khz t buf(min) bus free time between stop/start condition 0.12 1.3 s t hd,sta(min) hold time after (repeated) start condition 100 600 ns t su,sta(min) repeated start condition set-up time 30 600 ns t su,sto(min) stop condition set-up time 140 600 ns t hd,dat(min) data hold time (input) 30 100 ns t hd,dato data hold time (output) 300 600 900 ns t su,dat(min) data set-up time 30 600 ns t sp suppressed spike pulse width 50 110 250 ns t rst stuck-bus reset time scl or sda held low 25 32 40 ms c x scl, sda input capacitance sdai tied to sdao (note 5) 10 pf note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive, all voltages are referenced to gnd unless otherwise speci? ed. note 3: an internal clamp limits the gate pin to a minimum of 5v above source. driving this pin to voltages beyond the clamp may damage the device. note 4: integral nonlinearity is de? ned as the deviation of a code from a precise analog input voltage. maximum speci? cations are limited by the lsb step size and the single shot measurement. typical speci? cations are measured from 1/4, 1/2, 3/4 areas of the quantization band. note 5: guaranteed by design and not subject to test.
ltc4222 6 4222fa typical performance characteristics i dd1 vs v dd1 i dd2 vs v dd2 intv cc vs v dd2 intv cc vs i load v th(uv) vs temperature v hyst(uv) vs temperature t a = 25c. v ddn = 12v unless otherwise noted. v dd1 (v) 0 i dd1 (ma) 1.0 0.8 0.6 0.9 0.7 0.5 0.4 20 10 4222 g01 30 15 525 v dd2 (v) 0 i dd2 (ma) 4.0 3.0 3.5 2.5 2.0 20 10 4222 g02 30 15 525 v dd2 (v) 2.5 intv cc (v) 4.0 3.0 4222 g03 5.0 3.5 4.5 3.4 3.2 3.0 3.3 3.1 2.9 2.8 i load (ma) 0 intv cc (v) 7.5 2.5 4222 g04 15.0 5.0 10.0 12.5 3.50 3.00 3.25 2.75 2.50 v dd2 = 2.9v v dd2 = 3.3v v dd2 = 5v v dd2 = 12v temperature (c) C50 v th(uv) (v) 1.250 1.240 1.230 1.245 1.235 1.225 1.220 50 0 4222 g05 100 25 C25 75 temperature (c) C50 v hyst(uv) (mv) 100 90 95 85 80 50 0 4222 g06 100 25 C25 75 temperature (c) C50 i timer (a) 110 100 105 95 90 50 0 4222 g07 100 25 C25 75 i timer vs temperature
ltc4222 7 4222fa typical performance characteristics v gate vs temperature v gate vs i gate i gate vs temperature t a = 25c. v ddn = 12v unless otherwise noted. temperature (c) C50 v gate (v) 6.1 6.0 5.8 5.6 5.9 5.7 5.5 5.4 50 0 4222 g10 100 25 C25 75 v dd2 = 2.9v v dd2 = 3.3v v dd2 = 5v v dd2 = 12v i gate (a) 0 v gate (v) 6.5 6.0 4.5 5.5 5.0 4.0 10 46 4222 g11 14 8 212 v dd2 = 2.9v v dd2 = 3.3v v dd2 = 5v v dd2 = 12v temperature (c) C50 i gate (a) 12.0 11.9 11.7 11.8 11.6 11.5 50 0 4222 g12 100 25 C25 75 current limit vs v fb v th circuit breaker vs temperature v fb (v) 0 current limit (mv) 60 40 20 50 30 10 0 1.0 0.4 0.6 4222 g08 1.4 0.8 0.2 1.2 temperature (c) C50 v th circuit breaker (mv) 53 51 49 52 50 48 47 50 0 4222 g09 100 25 C25 75 i gpio (ma) 0 v gpio (v) 6 2 4222 g13 10 48 0.6 0.4 0.2 0.5 0.3 0.1 0 v dd2 = 2.9v v dd2 = 12v v ol(gpio) vs i gpio adc total unadjusted error vs code (adin1) code 0 error (%) 0 0.9 0.7 0.6 0.8 1.0 0.4 0.2 0.1 0.3 0.5 512 256 4222 g14 1024 768
ltc4222 8 4222fa typical performance characteristics t a = 25c. v ddn = 12v unless otherwise noted. v sense (mv) 0 t phl v gate (s) 100 10 1 0.1 4222 g18 400 350 300 250 200 150 100 50 adc inl vs code (adin1) adc dnl vs code (adin1) adc full-scale error vs temperature t phl v gate vs v sense overdrive temperature (c) C50 full-scale error (lsb) 4 3 2 0 C2 1 C1 C3 C4 50 0 4222 g17 100 25 C25 75 code 0 inl (lsb) 0.5 C0.4 0.4 0.2 0 C0.2 0.3 0.1 C0.1 C0.3 C0.5 512 256 4222 g15 1024 768 code 0 dnl (lsb) 0.5 C0.4 0.4 0.2 0 C0.2 0.3 0.1 C0.1 C0.3 C0.5 512 256 4222 g16 1024 768
ltc4222 9 4222fa pin functions adin: adc input. a voltage between 0 and 1.28v applied to this pin is measured by the on-board adc. tie to ground if unused. adr0, adr1, adr2: serial bus address inputs. tying these pins to ground, open, or intv cc con? gures one of 27 possible addresses. see table 1 in applications information. alert : fault alert output. open-drain logic output that is pulled to ground when a fault occurs to alert the host controller. a fault alert is enabled by setting the corre- sponding bit in the alert register as shown in table 4. see applications information. tie to ground if unused. config: con? guration input. con? gures the part to control the two channels together or independently. when config is tied to gnd both channels start up at the same time. a fault, en or on turn-off command on either channel will shut down both channels. when config is tied to intv cc , either channel can start up independently. a fault, en or on turn-off command will result in the associated chan- nel turning off, while the other channel remains on. if one channel is commanded to turn on while another channel is in the turn-on sequence, the ltc4222 waits until the ? rst channel has ? nished its turn-on sequence before turning on the second channel. en1 , en2 : enable input. ground this pin to indicate a board is present and enable the n-channel mosfet to turn-on. when this pin is high, the mosfet is not allowed to turn on. an internal 10a current source pulls up this pin. transitions on this pin are recorded in the fault register. a high-to-low transition activates the logic to read the state of the on pin and clear faults. see applications information. exposed pad: (pin 33, qfn package) exposed pad. may be left open or connected to device ground. fb1, fb2: foldback current limit and power-good input. a resistive divider from the output is tied to this pin. when the voltage at this pin drops below 1.235v, power is not considered good. the power bad condition may result in the gpio pin pulling low or going high impedance depending on the con? guration of control register bits 6 and 7. also a power bad fault is logged when the fb pin is low, the ltc4222 has ? nished the startup cycle and the gate pin is high. see applications information. the start-up current limit folds back from 50mv sense voltage to 16.6mv as the fb voltage drops from 0.8v to 0.2v. foldback is not active once the part leaves startup and the current limit is increased to 150mv. gate1, gate2: gate drive for external n-channel mosfet. an internal 12a current source charges the gate of the mosfet. no compensation capacitor is required on the gate pin, but a resistor and capacitor network from this pin to ground may be used to set the turn-on output volt- age slew rate. during turn-off there is a 1ma pull-down current. during a short circuit or undervoltage lockout (v dd or intv cc ), a 450ma pull-down current source between gate and source is activated. gnd: device ground. gpio1, gpio2: general purpose input/output. open-drain logic output or logic input. defaults to an output set to pull low to indicate power is not good. con? gure according to table 3. intv cc : low voltage supply decoupling output. connect a 0.1f capacitor from this pin to ground. on: (qfn package) on control input. formed by internally tying the on1 and on2 lines together. on1, on2: (ssop package) on control inputs. a rising edge turns on the external n-channel fet and a falling edge turns it off. this pin also con? gures the state of the fet on register bit (and hence the external fet) at power up. for example, if the on pin is tied high, then the fet on bit (control bit 3 in table 3) goes high 100ms after power-up. likewise if the on pin is tied low then the channel remains off after power-up until the fet on bit is set high using the i 2 c bus. a high-to-low transition on this pin clears the fault register for the related channel. the two on pins are tied together internally on the qfn package. ov1, ov2: overvoltage comparator input. connect this pin to an external resistive divider from v dd . if the voltage at this pin rises above 1.235v, an overvoltage fault is detected and the gate turns off. tie to gnd if unused.
ltc4222 10 4222fa scl: serial bus clock input. data at the sda pin is shifted in or out on rising edges of scl. this is a high impedance pin that is generally driven by an open-collector output from a master controller. an external pull-up resistor or current source is required. sdao: (ssop package) serial bus data output. open- drain output for sending data back to the master control- ler or acknowledging a write operation. normally tied to sdai to form the sda line. an external pull-up resistor or current source is required. internally tied to sdai in qfn package. sdai: (ssop package) serial bus data input. a high im- pedance input for shifting in address, command or data bits. normally tied to sdao to form the sda line. internally tied to sdao in qfn package. sda: (qfn package) serial bus data input/output line. formed by internally tying the sdao and sdai lines together. an external pull-up resistor or current source is required. sense1 C , sense2 C : negative current sense input. con- nect this pin to the output of the current sense resistor. the current limit circuit controls the corresponding gate pin voltage to limit the sense voltage between the sense + and sense C pins to the level set by the soft-start and foldback characteristic, with a maximum of 50mv during start-up and to 150mv independent of soft-start and foldback after the start-up timer has expired. a circuit breaker, enabled after start-up, trips when the sense voltage exceeds 50mv for 20s. sense1 + , sense2 + : (ssop package) positive current sense input. connect this pin to the input of the current sense resistor. it must be connected to the same trace as v ddn . internally tied to v ddn in the qfn package. source1, source2: n-channel mosfet source and adc input. connect this pin to the source of the external n-channel mosfet switch for gate drive return. this pin also serves as the adc input to monitor output voltage. the pin provides a return for the gate pull-down circuit. ss: soft-start input. sets the inrush current slew rate at start-up. connect a 68nf capacitor to provide 5mv/ms as the slew rate for the sense voltage in start-up. this cor- responds to 1a/ms with a 5m sense resistor. note that a large soft-start capacitor and a small timer capacitor may result in a condition where the timer expires before the inrush current has started. allow an additional 2nf of timer capacitance per 1nf of soft-start capacitor to ensure proper start-up. timer: start-up timer input. connect a capacitor be- tween this pin and ground to set a 12.3ms/f duration for start-up, after which an overcurrent fault is logged if the inrush is still current limited. the duration of the off time is 600ms/f when overcurrent auto-retry is enabled, resulting in a 1:50 duty cycle. an internal timer provides a 100ms start-up time and 5 second auto-retry time if this pin is tied to intv cc . allow an additional 2nf of timer capacitance per 1nf of soft-start (ss) capacitor to ensure proper start-up. uv1, uv2: undervoltage comparator input. connect this pin to an external resistive divider from v dd . if the volt- age at this pin falls below 1.145v, an undervoltage fault is detected and the gate turns off. pulling this pin below 0.4v resets the fault register for that channel except for the uv fault bit. tie to intv cc if unused. v dd1 , v dd2 : supply voltage input and positive current sense input. this pin has an undervoltage lockout threshold of 2.43v. in the qfn package this pin is also the positive current sense input. pin functions
ltc4222 11 4222fa functional diagram C + uv 1.235v uvs reset couple ovs v dd uvlo 0.4v 1.235v 1.235v intv cc 2.43v i 2 c 5 i 2 c addr uv C + rst 1.235v C + 0.2v 0.6v pwrgd fet on fault pg C + ov1 C + en en + C C + 1.235v C + 0.2v tm2 uvlo2 C + C + uvlo1 fb ov en 1.235v C + v dd 10 m a sdai (ssop) config ss sdao (ssop) sda (qfn) 1 of 27 2.64v v cc uvlo 4222 bd intv cc timer 2x 1x gpio intv cc v dd2 100 m a 1v 2 m a 10 bit 3.3v gen tm1 source gate C + cs C + cb sense + (ssop) sense C charge pump and gate driver foldback and didt 0mv to 150mv gp C + on adr2 adr1 adr0 ons 1.235v on source1 v dda C sense1 source2 v ddb C sense2 a/d converter scl alert + C 50mv + C adin1 adin2 logic soft-start
ltc4222 12 4222fa operation the ltc4222 is designed to turn two supply voltages on and off in a controlled manner, allowing boards to be safely inserted or removed from a live backplane. during normal operation, the charge pump and gate drivers turn on external n-channel mosfet gates to pass power to the loads. the gate driver circuits use a charge pump that derives its power from the v dd1 or v dd2 pin, whichever is higher. also included in the gate driver circuits are internal 6.5v gate-to-source clamps to protect the oxide of logic-level mosfets. during start-up the inrush currents are tightly controlled by using current limit foldback, soft- start di/dt limiting and output di/dt limiting. the ltc4222 is capable of controlling both channels independently, or coupling control signals so that both channels start up and turn off together. the current sense (cs) ampli? ers monitor the load cur- rents using the difference between the sense + (v dd for qfn) and sense C pin voltages. a cs ampli? er limits the current in the load by pulling back on the gate-to-source voltage in an active control loop when the sense voltage exceeds the commanded value. the cs ampli? ers require 20a input bias current from both the sense + and the sense C pins. a short circuit on an output to ground results in excessive power dissipation during active current limiting. to limit this power, the corresponding cs ampli? er regulates the voltage between the sense + and sense C pins at 150mv. if an overcurrent condition persists, the internal circuit breaker (cb) registers a fault when the sense voltage exceeds 50mv for more than 20s. this indicates to the logic that it is time to turn off the gate to prevent overheating. at this point the timer capacitor starts to discharge with the 2a current source until the voltage drops below 0.2v (comparator tm1) which tells the logic that the pass transistor has cooled and it is safe to turn on again if overcurrent auto-retry is enabled. if the timer pin is tied to intv cc , the cool-down time defaults to 5 seconds using an internal system timer. the output voltages are monitored using the fb resistive divider and the power good (pg) comparators to determine when output voltages are acceptable for the loads. the power good conditions are signaled by the gpio1 and gpio2 pins using open-drain pull-down transistors. the gpio pins may also be independently con? gured to signal power bad, or as general purpose inputs (gp comparators), or general purpose open-drain outputs. the functional diagram shows the monitoring blocks of the ltc4222. the group of comparators on the left side includes the undervoltage (uv), overvoltage (ov), reset (rst), enable ( en ) and on (on) comparators for chan- nel 1 or 2. these comparators determine if the external conditions are valid prior to turning on their correspond- ing gate. the two undervoltage lockout circuits, uvlo1 and uvlo2, validate the input supplies and the internally generated 3.3v supply, intv cc . uvlo2 also generates the power-up initialization to the logic circuits as intv cc crosses this rising threshold. the config pin is used to select the desired start-up behavior of the ltc4222. when the config pin is low, both channels will start up and turn off simultaneously and a fault on either channel will result in both channels turning off, or prevent both channels from starting up. t su, dat t su, sto t su, sta t buf t hd, sta t sp t sp t hd, dato, t hd, dati t hd, sta start condition stop condition repeated start condition start condition 4222 td01 sdai/sdao scl timing diagram
ltc4222 13 4222fa when the config pin is high the two channels work completely independently and ignore the behavior of the other channel. this allows for the channels to start up in sequence by connecting the gpio (power good) output of one channel to the uv pin of the other channel. the two channels share the timer and ss (soft-start) pins that control start-up behavior. if the config pin is high and one channel is enabled while the other channel is starting up, the ltc4222 will wait for the start-up cycle to end before starting up the second channel to ensure that it gets a full timer cycle. the exception to this is the on pins, which turn on the corresponding channel imme- diately. when both channels start up simultaneously, the inrush current for both channels is limited by whichever fb pin is lowest. included in the ltc4222 is a 10-bit a/d signal. the 6-input multiplexer ahead of the a/d converter allows to select between the two adin pins, the two source pins and the two current sense devices. an i 2 c interface is provided to read the a/d registers. it also allows the host to poll the device and determine if faults have occurred. if the alert line is con? gured as an interrupt, the host is enabled to respond to faults in real time. the sda line is divided into an sdai (input) and sdao (output). this simpli? es applications using an optoisolator driven directly from the sdao output. the i 2 c device address is forwarded to the address decoder from the adr0, adr1 and adr2 pins. these inputs have three states each that decode into a total of 27 device addresses. operation applications information a typical ltc4222 application is in a high availability system in which two positive voltage supplies are distributed to one or more cards. the device measures card voltages and currents and records past and present fault conditions for both channels. the system queries each ltc4222 over the i 2 c periodically and reads status and measurement information. a basic ltc4222 application circuit is shown in figure 1. the following sections cover turn-on, turn-off and acts upon various faults that the ltc4222 detects. external component selection is discussed in detail in the design example section. turn-on sequence the power supplies on a board are controlled by using external n-channel pass transistors (q1 and q2) placed in the power path. note that resistor r sn provides current detection. resistors r1n, r2n and r3n de? ne undervoltage and overvoltage levels for the two channels. r5n prevents high frequency oscillations in qn and r6n. c1n forms an optional network that may be used to provide an output dv/dt limited start-up. several conditions must be present before the external mosfet for a given channel turns on. first the external supplies, v ddn , must exceed their 2.44v undervoltage lockout levels. next the internally generated supply, intv cc , must cross its 2.64v undervoltage threshold. this gener- ates a 60s to 120s power-on-reset pulse. during reset the fault registers are cleared and the control registers are set or cleared as described in the register section. after a power-on-reset pulse, the ltc4222 goes through the following turn-on sequence for one or both channels. first the uv and ov comparators indicate that input power is within the acceptable range, which is indicated by status bits 0 to 1 in table 5. second, the en pin is externally pulled low. finally, all of these conditions must be satis? ed for the duration of 100ms to ensure that any contact bounce during insertion has ended. additionally, if the config pin is low all initial conditions for both channels must be met before the pair are allowed to turn on together. when these initial conditions are satis? ed, the on pin is checked and its state written to bit 3 in the control register (table 3). if it is high, the external mosfet is turned on. if the on pin is low, the external mosfet is turned on when the on pin is brought high or if a serial bus turn-on command is sent by setting control bit 3. if the config pin is low, either both on pins must be high or both control registers third bits must be set in order for the external mosfets to be turned on simultaneously.
ltc4222 14 4222fa figure 1. typical application a mosfet is turned on by charging up the gate with a 12a current source. when the gate voltage reaches the mosfet threshold voltage, the mosfet begins to turn on and the source voltage then follows the gate voltage as it increases. while the mosfet is turning on, the inrush current in- creases linearly at a di/dt rate selected by capacitor c ss . this is accomplished using the current limit ampli? er controlling the gate pin voltage. once the inrush current reaches the limit set by the fb pin, the di/dt ramp stops and the inrush current follows the foldback pro? le as shown in figure 2. when both channels turn on simultaneously, the foldback current limit is set by the lower of the two fb pins. a start-up timer is used to prevent damaging the mosfet when starting up into a short-circuit. the timer capacitor integrates at 100a during start-up and once the timer pin reaches threshold of 1.235v, the part checks to see if it is in current limit. if this is the case, the overcurrent fault bit, fault bit 2 in table 6, is set and the part turns off. if the part is not in current limit, the 50mv circuit breaker is armed and the current limit is switched to 150mv. alter- nately an internal 100ms start-up timer may be selected by tying the timer pin to intv cc . as the source voltage rises, the fb pin voltage follows as set by r7 and r8. once fb crosses its 1.235v threshold, and the start-up timer has expired, the corresponding gpio pin, in the default power good con? guration, ceases to pull low and indicates that power is now good. alternately status bit 3 can be read to check power-good status, where a zero indicates that power is good. if a series resistor and capacitor from gate to ground (r6 and c1) are employed to provide a constant inrush current during start-up, which provides a constant dv/dt at uv1 v dd1 ltc4222 gate1 intv cc adr2 adr1 nc adr0 config source1 uv2 v dd2 gate2 source2 ov1 ov2 alert scl sda on fb1 adin1 timer gpio1 en1 ss plug-in card r5-1 10 r g1 15k c g1 3.9nf c timer 0.68f c ss 68nf r s1 0.01 q1 fdd3706 r71 10.2k r81 3.57k r41 100k 4222 ta01a c f1 0.1f r11 140k r21 4.53k r31 13.7k z1 sa14a backplane gnd gnd alert scl on sda v in1 12v adin2 fb2 gpio2 en2 c3 0.1f r5-2 10 r g2 15k c g2 3.9nf r s2 0.01 q2 fdd3706 r72 4.99k r82 3.57k r42 100k c f2 0.1f r12 23.7k r22 3.32k r32 13.7k z2 sa14a v in2 3.3v sense1 C sense2 C applications information
ltc4222 15 4222fa applications information figure 2. power-up waveform v dd + 6v v gate v out gpio (power good) i load ? r sense v dd v sense 25mv 10mv ss limited fb limited 4222 f02 timer expires t startup the output, a 12a pull-up current (i gate ) from the gate pin slews the gate upwards and resulting current is less than the current limit. because the inrush current is less than the current limit, the start-up timer can expire without producing an overcurrent fault and a small timer capacitor may be used. after the timer has expired power good will not be signaled until the fb pin crosses its threshold and the gate-to-source voltage crosses the 4.3v threshold that indicates the mosfet is fully enhanced. when both those conditions are met the output voltage is suitable for the load to be turned on and the impedance back to the supply through the mosfet is low. power good is then asserted with the gpio pin or read via the interface, signaling that it is safe to turn on downstream loads. a power-bad fault is not generated when starting up in this manner because the fb pin will cross its threshold before the gate-to-source threshold is crossed. r g should be chosen such that i gate ? r g is less than the threshold of the mosfet to avoid a current spike at the beginning of startup. reducing r g degrades the stability of the current limit circuit, see applications information on current limit stability. gate pin voltage a curve of gate-to-source voltage vs v dd is shown in the typical performance characteristics. at minimum input supply voltage of 2.9v, the minimum gate-to-source drive voltage is 4.7v. the gate-to-source voltage is clamped below 6.5v to protect the gates of logic-level n-channel mosfets. turn-off sequence one or both gate pins are turned off by a variety of con- ditions. a normal turn-off is initiated by an on pin going low or a serial bus turn-off command. additionally, several fault conditions cause a gate to turn off. these include an input overvoltage (ov pin), input undervoltage (uv pin), overcurrent circuit breaker (sense C pin), or en transitioning high. writing a logic one into the uv, ov or oc fault bits (fault register bits 0 to 2 in table 6) also latches off the associated gate if their auto-retry bits are set to false. a mosfet is turned off with a 1ma current pulling down the gate pin to ground. with the mosfet turned off, the source and fb voltages drop as c l discharges. when the fb voltage crosses below its threshold, gpio may be con? gured to pull low to indicate that the output power is no longer good. if the intv cc pin drops below 2.60v for greater than 1s, or the associated v dd pin falls below 2.35v for greater than 2s, a fast shut down of the mosfet is initiated. in this case the gate pin is pulled down with a 450ma current to the source pin. overcurrent fault the ltc4222 has different current limiting behavior during start-up, when the output supply ramps up under timer, ss and fb control, and normal operation. as such it can generate an overcurrent fault during both phases of op- eration. both set the faulting supplys overcurrent fault bit (fault register bit 2) and shut off the faulting gate, or both gates if the config pin is low. during start-up when both timer and ss are ramping, the current limit is a function of ss pin voltage and the voltage on the fb pins. a supply could power up entirely in current limit depending on the bypass capacitor at the outputs of the ramping supplies. the timer pin sets the time duration for current limit during start-up, either 12.3ms/f when using a timer capacitor, or 100ms when the timer pin is tied to intv cc . if the supply is still in current limit at the end of the timing cycle, an overcurrent
ltc4222 16 4222fa applications information fault is declared for that supply and the mosfet is turned off. if the config pin is low, then both channels will turn off together. after the switch has turned off due to an oc fault the part will wait for a cool-down period before allowing the switch to turn on again. if the timer pin is tied to v cc the cool-down period will be 5 seconds on the internal timer. otherwise if using a timer capacitor, the capacitor will discharge at 2a and the internal 100ms timer is started, when the 100ms timer expires and the timer pin reaches its 0.2v lower threshold the part is allowed to restart if the overcurrent fault bit (fault register bit 2) has been cleared or the overcurrent auto-retry bit (control register bit 2) has been set. after start-up, a supply has dual-level glitch-tolerant protec- tion against overcurrent faults. the sense resistor voltage drop is monitored by a 50mv electronic circuit breaker and a 150mv active current limit. in the event that a supplys current exceeds the circuit breaker threshold, an internal 20s timer is started. if the supply is still overcurrent after 20s the circuit breaker trips and the switch is turned off. an analog current limit loop prevents the supply current from exceeding exceeding the 150mv current limit in the event of a short circuit. the 20s ? lter delay and the higher current limit threshold prevent unnecessary resets of the board due to minor current surges. the ltc4222 will stay in the latched off state unless the overcurrent auto-retry bit (control register bit 2) is set, in which case the switch turns on again after 100ms when using the external timer capacitor to set the start-up time, or 5 seconds when using the internal timer. note that current limit foldback is not active after start-up. overvoltage fault an overvoltage fault occurs when an ov pin rises above its 1.235v threshold for more than 2s. this shuts off the corresponding gate with a 1ma current to ground and sets the overvoltage present status bit 0 and the overvoltage fault bit 0. if the pin subsequently falls back below the threshold for 100ms, the gate is allowed to turn on again unless overvoltage auto-retry has been disabled by clearing control bit 0. if the config pin is tied low, an ov fault on either channel will shut off both channels simultaneously. undervoltage fault an undervoltage fault occurs when a uv pin falls below its 1.235v threshold for more than 2s. this turns off the corresponding gate with a 1ma current to ground and sets undervoltage present status bit 1 and undervoltage fault bit 1. if the uv pin subsequently rises above the threshold for 100ms, the gate is turned on again unless undervoltage auto-retry has been disabled by clearing control bit 1. when power is applied to the device, if uv is below its 1.235v threshold after intv cc crosses its 2.64v undervoltage lockout threshold, an undervoltage fault is logged in the fault register. if the config pin is tied low, an uv fault on either channel will shut off both channels simultaneously. on signals and the config pin turn-on commands are issued from the on pins or the i 2 c interface. internally, rising and falling edges of the on pins set and reset the fet_on register bits. unlike the other control signals such as uv, ov and en , the rising edge of the on signal is not ? ltered by the 100ms internal timer and instead turns on the corresponding channel immediately. cycling an on signal cancels the corresponding channels overcurrent auto-retry cool-down period, allowing the channel to restart after a 100ms delay. to start up and shut down both channels at the same time set the config pin low. both channels then start up when all the uv, ov, en and on signals are in the correct state to turn on both channels, and when any of these signals turns one channel off, both channels turn off. figure 3. short-circuit waveform v gpio 5v/div v gate 10v/div c l = 0f r short = 5m r s = 20m r g = 1k c g = 1f v source 10v/div load current 5a/div 4222 f03 10s/div
ltc4222 17 4222fa applications information setting the config pin high allows the two channels to start up and turn off independently. when both on signals are brought high sequentially, the channel turned on ? rst immediately begins to start up and the second channel has a 200ns window to assert its on signal in order to start up in the same timer period. if the second on signal is asserted after the 200ns window but before the end of the ? rst channels start-up time, the second channel start- up is delayed. the second channel will then start 100ms after the ? rst channels start-up timer has expired and the timer pin, if used, reaches its 200mv low threshold. when an external timer capacitor is used, the timer capacitor voltage ramps up with a 100a current. once the timer pin reaches its 1.235v threshold the timer begins to discharge. while the timer capacitor is discharging, the on signal for the second channel should not be asserted for 2ms/f of timer capacitance. this allows the timer capacitor to return to its low state and ensures that the next channel to start receives a full timer cycle. this wait time is unnecessary when using the internal 100ms timer. board present change of state the en pins may be used to detect the presence of one or two downstream cards. whenever an en pin toggles, fault bit 4 is set to indicate a change of state. when the en pin goes high, indicating board removal, the corresponding gate turns off immediately (with a 1ma current to ground) and the board present status bit 4, is cleared. if the en pin is pulled low, indicating a board insertion, all fault bits for that channel except fault bit 4 are cleared and enable status bit 4, is set. if the en pin remains low for 100ms the state of the on pin is captured in fet on control bit 3. this turns the switch on if the on pin is tied high. there is an internal 10a pull-up current source on the en pin. if the config pin is tied low, both en pins must be low for 100ms for the two channels to be enabled and if either en pin goes high both channels will turn off. if a channel shuts down due to a fault, it may be desirable to restart that channel simply by removing and reinserting the related load card. in cases where the ltc4222 and the switch reside on a backplane or midplane and the load resides on a plug-in card, the en pin detects when the plug-in card is removed. figure 4 shows an example where the en pin is used to detect insertion. once the plug-in card is reinserted the fault register is cleared except for fault bit 4. after 100ms the state of the on pin is latched into bit 3 of the control register. at this point the channel starts up again. if a connection sense on the plug-in card is driving an en pin, insertion or removal of the card may cause the pin voltage to bounce. this results in clearing the fault register when the card is removed. the pin may be debounced using a ? lter capacitor, c en , on the en pin as shown in figure 4. the ? lter time is given by: t filter = c en ? 123 (ms/f) figure 4. plug-in card insertion/removal C + 1.235v gnd motherboard connector plug-in card source out ltc4222 10a en c en load 4222 f04 fet short fault a fet short fault is reported if the data converter measures a current sense voltage greater than or equal to 2mv while the corresponding gate is turned off. this condition sets fet short bit, fault bit 5. power-bad fault a power-bad fault is reported if a fb pin voltage drops below its 1.235v threshold for more than 2s when the corresponding gate is above the 4.3v gate to source threshold. this pulls the gpio pin low immediately in the default power good con? guration, and sets power-bad present bit, status bit 3, and power-bad bit, fault bit 3. a circuit prevents power-bad faults if the gate-to-source voltage is low, eliminating false power-bad faults during power-up or power-down. if the fb pin voltage subsequently rises back above the threshold, a power good con? gured gpio pin returns to a high impedance state and status bit 3 is reset.
ltc4222 18 4222fa applications information fault alerts when any of the fault bits in a fault register (see table 4) are set, an optional bus alert is generated if the appropri- ate bit in the alert register has been set. this allows only selected faults to generate alerts. at power-up the default state is to not alert on faults and the alert pin is high. if an alert is enabled, the corresponding fault causes the alert pin to pull low. after the bus master controller broadcasts the alert response address, the ltc4222 responds with its address on the sda line and releases alert as shown in table 7. if there is a collision between two ltc4222s responding with their addresses simultaneously, then the device with the lower address wins arbitration and responds ? rst. the alert line is also released if the device is addressed by the bus master if alert is pulled low due to an alert. once the alert signal has been released for one fault, it is not pulled low again until the fault register indicates a different fault has occurred or the original fault is cleared and it occurs again. note that this means repeated or continuing faults do not generate alerts until the associ- ated fault register bit has been cleared. resetting faults faults are reset with any of the following conditions on a given channel. first, a serial bus command writing zeros to the fault register bits 0 to 5 clears the associated faults. second, fault register bits 0 to 5 are cleared when the corresponding switch is turned off by the on pin or status bit 3 going from high to low, if the corresponding uv pin is brought below its 0.4v reset threshold for 2s, or if intv cc falls below its 2.64v undervoltage lockout threshold. finally, when en is brought from high to low, only corresponding fault bits 0-3 and 5 are cleared, and bit 4, which indicates a en change of state, is set. note that faults that are still present, as indicated in the status registers, cannot be cleared. the fault registers are not cleared when auto-retrying. when auto-retry is disabled the existence of an overvoltage, undervoltage, or overcurrent fault keeps the switch off. as soon as the fault is cleared, the switch turns on. if auto-retry is enabled, then a high value in status register bits 0 or 1 holds the switch off and the fault register is ignored. subsequently, when status register bits 0 and 1 are cleared by removal of the fault condition, the switch is allowed to turn on again. the ltc4222 will set fault bit 2 and turn off in the event of an overcurrent fault, preventing it from remaining in an overcurrent condition. if con? gured to auto-retry, the ltc4222 will continually attempt to restart after cool-down cycles until it succeeds in starting up without generating an overcurrent fault. note that if a switch is on after an auto-retry and the fault bit has not been reset, clearing the corresponding auto-retry bit will turn the channel off. data converter the ltc4222 incorporates a 10-bit a/d converter that continuously scans six different voltages. the source pins have a 1/24 resistive divider to monitor a full-scale voltage of 32v with 31.25mv resolution. the adin pins are monitored with a 1.28v full scale and 1.25mv resolution, and the voltage between the v dd and sense pins is moni- tored with a 64mv full scale and 62.5v resolution. results from each conversion are stored, left justi? ed, in registers as seen in tables 7 and 8, and are updated 15 times per second. setting adc_control register bit 0 invokes a test mode that halts the data converter so that the data converter result registers may be written to and read from for software testing. the data converter also has a direct address mode that allows the user to take a speci? c measurement at a spe- ci? c time and hold that value for later readback. direct address mode is entered by setting the halt bit, bit 0, in the adc_control register (see table 9). then when the channel address bits, adc_control bits 1 to 3, are written to, the adc will make a single measurement on the channel indicated by those bits, then stop. setting the adc alert bit, adc_control bit 4, will enable an interrupt when the data converter ? nishes the conversion, result- ing in the alert pin pulling low when the data is ready. alternately, the adc busy bit, adc_control bit 5, can be polled to check for the end of the conversion, after a direct address conversion the adc busy bit will go low. in normal mode adc busy is always high. resetting the halt bit returns the data converter to the scan mode.
ltc4222 19 4222fa applications information con? guring the gpio pins table 3 describes the possible states of the gpio pins using the control registers bits 6 and 7. at power-up, the default state is for a gpio pin to go high impedance when power is good (fb pin greater than 1.235v). other applications for a gpio pin are to pull down when power is good, a general purpose output and a general purpose input. a simple application of the gpio pin in the power good con? guration is to connect it to the uv pin of the other channel with the config pin high. this will result in the second channel being turned on after the ? rst channel has started up and signaled power good. current limit stability for many applications the ltc4222 current limit will be stable without additional components. however there are certain conditions where additional components may be needed to improve stability. the dominant pole of the cur- rent limit circuit is set by the capacitance and resistance at the gate of the external mosfet, and larger gate capaci- tance makes the current limit loop more stable. usually a total of 8nf gate to source capacitance is suf? cient for stability and is typically provided by inherent mosfet c gs , however the stability of the loop is degraded by increasing r sense or by reducing the size of the resistor on a gate rc network if one is used, which may require additional gate to source capacitance. board level short-circuit testing is highly recommended as board layout can also affect transient performance, for stability testing the worst-case condition for current limit stability occurs when the output is shorted to ground after a normal start-up. there are two possible parasitic oscillations when the mosfet operates as a source follower when ramping at power-up or during current limiting. the ? rst type of oscillation occurs at high frequencies, typically above 1mhz. this high frequency oscillation is easily damped with r5 as shown in figure 1. in some applications, one may ? nd that r5 helps in short-circuit transient recovery as well. however, too large of an r5 value will slow down the turn-off time. the recommended r5 range is between 5 and 500. the second type of source follower oscillation occurs at frequencies between 200khz and 800khz due to the load capacitance being between 0.2f and 9f, the presence of r5 resistance, the absence of a drain bypass capacitor, a combination of bus wiring inductance and bus supply output impedance. to prevent this second type of oscillation avoid load capacitance below 10f, alternately connect an external capacitor from the mosfet gate to ground with a value greater than 1.5nf. supply transients the ltc4222 is designed to ride through supply transients caused by load steps. if there is a shorted load and the parasitic inductance back to the supply is greater than 0.5h, there is a chance that the supply collapses before the active current limit circuit brings down the gate pin. if this occurs, the undervoltage monitors pull the corre- sponding gate pin low. the undervoltage lockout circuit has a 2s ? lter time after v dd drops below 2.35v. the uv pin reacts in 2s to shut the gate off, but it is recom- mended to add a ? lter capacitor, c f , to prevent unwanted shutdown caused by a transient. eventually either the uv pin or undervoltage lockout responds to bring the current under control before the supply completely collapses. supply transient protection the ltc4222 is safe from damage with supply voltages up to 35v. however, spikes above 35v may damage the part. during a short-circuit condition, large changes in current ? owing through power supply traces may cause induc- tive voltage spikes which exceed 35v. to minimize such spikes, the power trace inductance should be minimized by using wider traces or heavier trace plating. also, a snubber circuit dampens inductive voltage spikes. build a snubber by using a 100 resistor in series with a 0.1f capacitor between v dd and gnd. a surge suppressor, z1 in figure 1, at the input can also prevent damage from voltage surges. design example as a design example, take the following speci? cations for channel 1: v in = 12v, i max = 5a, i inrush = 1a, di/dt inrush = 10a/ms, c l = 330f, v uv(rising) = 10.75v, v ov(falling) = 14.0v, v pwrgd(up) = 11.6v, and i 2 c address = 1000111. this completed design is shown in figure 1.
ltc4222 20 4222fa applications information selection of the sense resistor, r s , is set by the overcurrent threshold of 50mv: r mv i s max == 50 001 . the mosfet is sized to handle the power dissipation dur- ing inrush when output capacitor c out is being charged. a method to determine power dissipation during inrush is based on the principle that: energy in c l = energy in q1 this uses: energy in c cv mf l == 1 2 1 2 033 12 22 (. )( ) or 0.024 joules. calculate the time it takes to charge up c out : t cvi i mf v a startup l dd inrush inrush === ? .? 033 12 1 4 4ms the power dissipated in the mosfet: p t w diss startup == energy in c l 6 the soa (safe operating area) curves of candidate mosfets must be evaluated to ensure that the heat capacity of the package tolerates 6w for 4ms. the soa curves of the fairchild fdc653n provide for 2a at 12v (24w) for 10ms, satisfying this requirement. since the fdc653n has less than 8nf of gate capacitance and we are using a gate rc network, the short-circuit stability of the current limit should be checked and improved by adding a capacitor from gate to source if needed. the inrush current is set to 1a using c1: c ci i lgate inrush 1 = ? c mf a a cnf 1 033 12 1 139 == .? . or the inrush di/dt is set to 10a/ms using c ss : c i r a ss ss sense = ? ? ? ? ? ? = dl/dt a s ?. ? ?. 0 0429 1 10 0 0 0429 1 10000 0 01 43 ? ?. . = nf choose 4.7nf for a start-up time of 4ms with a 2x safety margin we choose: c t c c ms timer startup ss timer =+ = 2 2 8 ? ? 12.3ms/f 1 2 2.3ms/f f += 47 2 068 .? . nf note the minimum value of c timer is 10nf. the uv and ov resistor string values can be solved in the following method. first pick r3 based on i string being 1.235v/r3 at the edge of the ov rising threshold. then solve the following equations: r v v r uv ov ov off uv on th rising th fall 23 = () () () ( ?? i ing r ) C3 r vrr uv rr uv on th rising 1 32 32 = + () () ?( ) CC in our case we choose r3 to be 3.4k to give a resistor string current below 100a. then solving the equations results in r2 = 1.16k and r1 = 34.6k. the fb divider is solved by picking r8 and solving for r7, choosing 3.57k for r8 we get: r vr fb r pwrgd up th rising 7 8 8 = () () ? C resulting in r7 = 30k a 0.1f capacitor, c f , is placed on the uv pins to prevent supply glitches from turning off the gate via uv or ov.
ltc4222 21 4222fa applications information the address is set with the help of table 1, which indi- cates binary address 1000111 corresponds to address 4. address 4 is set by setting adr2 low, adr1 open and adr0 high. next the value of r5 and r6 are chosen to be the default values 10 and 15k as discussed previously. in addition a 0.1f ceramic bypass capacitor is placed on the intv cc pin. layout considerations to achieve accurate current sensing, a kelvin connection is required. the minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. using 0.03" per amp or wider is recommended. note that 1oz copper exhibits a sheet resistance of about 530?. small resistances add up quickly in high current applications. to improve noise immunity, put the resistive dividers to the uv, ov and fb pins close to the device and keep traces to v dd and gnd short. it is also important to put the bypass capacitor for the intv cc pin, c3, as close as possible between intv cc and gnd. 0.1f capacitors from the uv pins (and ov pins through resistor r2) to gnd also helps reject supply noise. figure 5 shows a layout that addresses these issues. note that surge suppressor, z1 is placed between supply and ground using wide traces. digital interface the ltc4222 communicates with a bus master using a 2-wire interface compatible with i 2 c bus and smbus, an i 2 c extension for low power devices. the ltc4222 is a read-write slave device and supports smbus bus read byte, write byte, read word and write word commands. a complete list of the resistors of the ltc4222 is shown in table 2. the second word in a read word command is the contents of the subsequent 8-bit register. the second word in a write word command is ignored. data formats for these commands are shown in figures 6 to 11. the ltc4222 interface also features a 25ms timeout feature to prevent the bus being stuck low if a communication error occurs. if either the scl or sda lines remain low for more than 25ms the ltc4222 will reset its interface and release the sdao pin, freeing the bus to resume communication. the ltc4222 also features pmbus compatibility, the in- terface will not acknowledge unsupported commands and the internal addresses are in the manufacturer speci? ed address space under the pmbus speci? cation. start and stop conditions when the bus is idle, both scl and sda are high. a bus master signals the beginning of a transmission with a start condition by transitioning sda from high to low while scl is high, as shown in figure 6. when the master has ? nished communicating with the slave, it issues a stop condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission. i 2 c device addressing twenty seven distinct bus addresses are available using three 3-state address pins, adr0, adr1 and adr2. table 1 shows the correspondence between pin states and ad- dresses. in addition, the ltc4222 responds to two special addresses. address (1100 0110) is a mass write address that writes to all ltc4222s, regardless of their individual address settings. mass write can be disabled by setting register bit 4 in the control register of channel 2 to zero. address (0001 100) is the smbus alert response address. if the ltc4222 is pulling low on the alert pin due to an figure 5. recommended layout ss config intv cc gnd ov uv v dd sense + sense C ltc4222uhd 4222 f05 vias to ground plane via to ground plane sense resistor r s i load c ss c3 r2 r3 c f z1 r1
ltc4222 22 4222fa applications information s address a7:a0 4222 f07 from master to slave from slave to master a: acknowledge (low) a : not acknowledge (high) r: read bit (high) w : write bit (low) s: start condition p: stop condition command data b7:b0 0 w 000 b7:b0 a a ap s address a7:a0 command data data b7:b0 0 w 000 0 4222 f08 x x x x x x x x b7:b0 a a a ap s address a7:a0 a7:a0 1 0 command s address r a b7:b0 1 data b7:b0 0 w 00 4222 f09 a a a p figure 7. ltc4222 serial bus sda write byte protocol figure 8. ltc4222 serial bus sda write word protocol figure 9. ltc4222 serial bus sda read byte protocol figure 6. data transfer over i 2 c or smbus scl sda start condition stop condition address r/ w ack data ack data ack 1 - 7 8 9 4222 f06 a6 - a0 b7 - b0 b7 - b0 1 - 7 8 9 1 - 7 8 9 p s alert, it acknowledges this address by broadcasting its address and releasing the alert pin. acknowledge the acknowledge signal is used in handshaking between transmitter and receiver to indicate that the last byte of data was received. the transmitter always releases the sda line during the acknowledge clock pulse. when the slave is the receiver, it pulls down the sda line so that it remains low during this pulse to acknowledge receipt of the data. if the slave fails to acknowledge by leaving sda high, then the master may abort the transmission by generating a stop condition. when the master is receiving data from the slave, the master pulls down the sda line during the clock pulse to indicate receipt of the data. after the last byte has been received the master leaves the sda line high (not acknowledge) and issues a stop condition to terminate the transmission. write protocol the master begins communication with a start con- dition followed by the seven bit slave address and the r/w bit set to zero, as shown in figure 7. the addressed ltc4222 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to write. the ltc4222 acknowledges this and then latches the lower three bits of the command byte into its internal register address pointer. the master then delivers the data byte and the ltc4222 acknowledges once more and latches the data into its control register. the transmission is ended when the master sends a stop condition. if the master continues sending a second data byte, as in a write word command, the second data byte is acknowledged by the ltc4222 but ignored, as shown in figure 8. read protocol the master begins a read operation with a start con- dition followed by the seven bit slave address and the r/w bit set to zero, as shown in figure 9. the addressed ltc4222 acknowledges this and then the master sends a command byte which indicates which internal register the master wishes to read. the ltc4222 acknowledges this and then latches the lower three bits of the command byte into its internal register address pointer. the master then sends a repeated start condition followed by the
ltc4222 23 4222fa s alert response address 0 0 0 1 1 0 0 device address a7:a0 1 1 r 0 4222 f11 a a p s address a7:a0 a7:a0 1 0 command s address r a b7:b0 1 data b7:b0 0 w 00 4222 f10 a 0 a b7:b0 data a a p figure 10. ltc4222 serial bus sda read word protocol figure 11. ltc4222 serial bus sda alert response protocol applications information same seven bit address with the r/w bit now set to one. the ltc4222 acknowledges and send the contents of the requested register. the transmission is ended when the master sends a stop condition. if the master acknowledges the transmitted data byte, as in a read word command, figure 10, the ltc4222 repeats the requested register as the second data byte. alert response protocol when any of the fault bits in the fault register are set, an optional bus alert is generated if the appropriate bit in the alert register is also set. if an alert is enabled, the corresponding fault causes the alert pin to pull low. after the bus master controller broadcasts the alert response address, the ltc4222 responds with its address on the sda line and then release alert as shown in figure 11. the alert line is also released if the device is addressed by the bus master. the alert signal is not pulled low again until the fault register indicates a different fault has occurred or the original fault is cleared and it occurs again. note that this means repeated or continuing faults do not generate alerts until the associated fault register bit has been cleared.
ltc4222 24 4222fa applications information table 1. ltc4222 i 2 c device addressing description device address device address lt c 4 2 2 2 address pins h 76543210adr2adr1adr0 mass write c6 11000110xxx alert response 19 00011001xxx 0 88 1000100xlncl 1 8a 1000101xlhnc 2 8c 1000110xlncnc 3 8e 1000111xlnch 4 98 1001100xlll 5 9a 1001101xlhh 6 9c 1001110xllnc 7 9e 1001111xllh 8 a8 1010100xncncl 9 aa 1010101xnchnc 10 ac 1010110xncncnc 11 ae 1010111xncnch 12 b8 1011100xncll 13 ba 1011101xnchh 14 bc 1011110xnclnc 15 be 1011111xnclh 16 c8 1100100xhncl 17 ca 1100101xhhnc 18 cc 1100110xhncnc 19 ce 1100111xhnch 20 d8 1101100xhll 21 da 1101101xhhh 22 dc 1101110xhlnc 23 de 1101111xhlh 24 e8 1110100xlhl 25 ea 1110101xnchl 26 ec 1110110xhhl
ltc4222 25 4222fa applications information table 2. ltc4222 register addresses and contents register address register name description decimal hex 208 d0h control1 (a1) sets behavior for channel 1 209 d1h alert1 (b1) selects which channel 1 faults generate alerts 210 d2h status1 (c1) displays the status of channel 1 211 d3h fault1 (d1) fault log for channel 1 212 d4h control2 (a2) sets behavior for channel 2 213 d5h alert2 (b2) selects which channel 2 faults generate alerts 214 d6h status2 (c2) displays the status of channel 2 215 d7h fault2 (d2) fault log for channel 2 216 d8h source1 msb adc source1 msb data 217 d9h source1 lsb adc source1 lsb data 218 dah source2 msb adc source2 msb data 219 dbh source2 lsb adc source2 lsb data 220 dch adin1 msb adc adin1 msb 221 ddh adin1 lsb adc adin1 lsb 222 deh adin2 msb adc adin2 msb 223 dfh adin2 lsb adc adin2 lsb 224 e0h sense1 msb adc sense1 msb 225 e1h sense1 lsb adc sense1 lsb 226 e2h sense2 msb adc sense2 msb 227 e3h sense2 lsb adc sense2 lsb 228 e4h adc control con? gures behavior of the adc + set bit adc_control(0) before writing
ltc4222 26 4222fa applications information table 3. control registers a C read/write bit control 1 (d0h) control 2 (d4h) operation 7:6 gpio1 con? gure gpio2 con? gure function a6 a7 gpio pin power good (default) 0 0 gpio = c3 power ? good 0 1 gpio = c3 general purpose output 1 0 gpio = a5 general purpose input 1 1 c6 = gpio 5 gpio1 output gpio2 output output data for gpio pins when con? gured as general purpose output 1 = high impedance, 0 = pulled low 4 reserved mass write enable allows mass write addressing 1 = mass write enabled (default), 0 = mass write disabled 3 channel 1 fet on control channel 2 fet on control on control bit, latches the state of the on pin at the end of the debounce delay 1 = fet on, 0 = fet off 2 channel 1 overcurrent auto-retry channel 2 overcurrent auto-retry overcurrent auto-retry bit 1 = auto-retry after overcurrent, 0 = latch off after overcurrent (default) 1 channel 1 undervoltage auto-retry channel 2 undervoltage auto-retry undervoltage auto-retry 1 = auto-retry after undervoltage (default), 0 = latch off after undervoltage 0 channel 1 overvoltage auto-retry channel 2 overvoltage auto-retry overvoltage auto-retry 1 = auto-retry after overvoltage (default), 0 = latch off after overvoltage table 4. alert registers b C read/write bit alert 1 (d1h) alert 2 (d5h) operation 7 reserved reserved not used 6 reserved reserved not used 5 channel 1 fet short alert channel 2 fet short alert enables alert for fet short condition 1 = enable alert, 0 = disable alert (default) 4 en1 state change alert en2 state change alert enables alert when en changes state 1 = enable alert, 0 = disable alert (default) 3 channel 1 power bad alert channel 2 power bad alert enables alert when output power is bad 1 = enable alert, 0 = disable alert (default) 2 channel 1 overcurrent alert channel 2 overcurrent alert enables alert for overcurrent condition 1 = enable alert, 0 = disable alert (default) 1 channel 1 undervoltage alert channel 2 undervoltage alert enables alert for undervoltage condition 1 = enable alert, 0 = disable alert (default) 0 channel 1 overvoltage alert channel 2 overvoltage alert enables alert for overvoltage condition 1 = enable alert, 0 = disable alert (default)
ltc4222 27 4222fa applications information table 5. status registers c C read bit status 1 (d2h) status 2 (d6h) operation 7 fet on fet on 1 = fet on, 0 = fet off 6 gpio1 input gpio2 input reports the state of the gpio1 pin 1 = gpio1 high, 0 = gpio1 low 5 channel 1 fet short status channel 2 fet short status reports the state of the gpio2 pin 1 = gpio2 high, 0 = gpio2 low 4 en1 status en2 status indicates if the channel is enabled when en is low 1 = en pin low, 0 = en pin high 3 channel 1 power bad channel 2 power bad indicates power is bad when fb is low 1 = fb low, 0 = fb high 2 channel 1 overcurrent channel 2 overcurrent indicates overcurrent condition; 1 = overcurrent, 0 = not overcurrent 1 channel 1 undervoltage channel 2 undervoltage indicates input undervoltage when uv is low 1 = uv low, 0 = uv high 0 channel 1 overvoltage channel 2 overvoltage indicates input overvoltage when ov is high 1 = ov high, 0 = ov low table 6. fault registers d C read/write bit fault 1 (d3h) fault 2 (d7h) operation 7 reserved reserved reserved 6 reserved reserved reserved 5 channel 1 fet short fault occurred channel 2 fet short fault occurred indicates potential fet short was detected when measured current sense voltage exceeded 1mv while fet was off 1 = fet was shorted, 0 = fet is good 4 channel 1 en changed state channel 2 en changed state indicates that the ltc4215-1 was enabled or disabled when en changed state 1 = en changed state, 0 = en unchanged 3 channel 1 power bad fault occurred channel 2 power bad fault occurred indicates power was bad when fb went low 1 = fb was low, 0 = fb was high 2 channel 1 overcurrent fault occurred channel 2 overcurrent fault occurred indicates overcurrent fault occurred 1 = overcurrent fault occurred, 0 = no overcurrent faults 1 channel 1 undervoltage fault occurred channel 2 undervoltage fault occurred indicates input undervoltage fault occurred when uv went low 1 = uv was low, 0 = uv was high 0 channel 1 overvoltage fault occurred channel 2 overvoltage fault occurred indicates input overvoltage fault occurred when ov went high 1 = ov was high, 0 = ov was low
ltc4222 28 4222fa table 7. adc register data format: adinn, sourcen, sensen msb bytes C read/write* bit (7) bit (6) bit (5) bit (4) bit (3) bit (2) bit (1) bit (0) data (9) data (8) data (7) data (6) data (5) data (4) data (3) data (2) *set bit adc _control(0) before writing table 8. adc register data format: adinn, sourcen, sensen lsb bytes C read/write* bit (7) bit (6) bit (5) bit (4) bit (3) bit (2) bit (1) bit (0) data (1) data (0) reserved** reserved** reserved** reserved** reserved** reserved** *set bit adc _control(0) before writing **read as zero applications information table 9. adc control register e C read/write bit adc_control (e4h) operation 7 reserved reserved 6 reserved reserved 5 adc busy status bit that is high when the adc is converting. always high in free-run mode, low when adc is halted or after a point and shoot conversion. read only 4 adc alert enables the alert pin to pull low when the adc finishes a measurement 3 adc channel address these bits may be written to cause the adc to make a single measurement of the desired channel when the halt bit is high function sf2-0 source1 000 source2 001 adin1 010 adin2 011 sense1 100 sense2 101 2 1 0 halt stops the data converter and enables point and shoot mode
ltc4222 29 4222fa typical applications figure 12. 3.3v and 12v application with sequenced turn-on optically isolated i 2 c communication and 5a current limits. schottky diode allows 3.3v switch to turn on when 12v is absent uv1 v dd1 ltc4222 gate1 intv cc adr2 adr1 nc adr0 config source1 uv2 v dd2 gate2 source2 ov1 ov2 alert scl sda0 sda1 fb1 adin1 timer intv cc intv cc gpio1 en1 ss plug-in card r5-1 10 r6-1 15k r10 3.3k c1-1 22nf c ss 68nf r s1 0.01 q1 fdd3706 r7-1 10.2k r8-1 3.57k r4-1 100k 4222 ta03 c f1 0.1f r1-1 34k r2-1 1.02k r3-1 3.4k z1 sa14a bat 254 backplane scl gnd gnd sda 5v v in1 12v adin2 fb2 gpio2 en2 c3 0.1f r5-2 10 r6-2 15k c1-2 22nf r s2 0.01 q2 fdd3706 r7-2 4.99k r8-2 3.57k c f2 0.1f r1-2 6.55k r2-2 1.02k r3-2 3.4k z2 sa14a v in2 3.3v on2 on1 6 5 2 3 hcpl-0300 5v 2 8 8 3 6 5 hcpl-0300 r9 10k intv cc r10 3.3k 5v 28 3 6 5 hcpl-0300 r12 10k intv cc sense1 C sense2 C
ltc4222 30 4222fa package description uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 31 1 2 32 bottom viewexposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05
ltc4222 31 4222fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description g package 36-lead plastic ssop (5.3mm) (reference ltc dwg # 05-08-1640) g36 ssop 0204 0.09 C 0.25 (.0035 C .010) 0 C 8 0.55 C 0.95 (.022 C .037) 5.00 C 5.60** (.197 C .221) 7.40 C 8.20 (.291 C .323) 1234 5 6 7 8 9 10 11 12 14 15 16 17 18 13 12.50 C 13.10* (.492 C .516) 25 26 22 21 20 19 23 24 27 28 29 30 31 32 33 34 35 36 2.0 (.079) max 0.05 (.002) min 0.65 (.0256) bsc 0.22 C 0.38 (.009 C .015) typ millimeters (inches) dimensions do not include mold flash. mold flash shall not exceed .152mm (.006") per side dimensions do not include interlead flash. interlead flash shall not exceed .254mm (.010") per side * ** note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale 0.42 0.03 0.65 bsc 5.3 C 5.7 7.8 C 8.2 recommended solder pad layout 1.25 0.12
ltc4222 32 4222fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0309 rev a ? printed in usa related parts typical application part number description comments ltc1642a single channel, hot swap controller operates from 3v to 16.5v, overvoltage protection up to 33v, ssop-16 ltc1645 dual channel, hot swap controller operates from 3v to 12v, power sequencing, so-8 or so-14 ltc1647-1/ltc1647-2/ ltc1647-3 dual channel, hot swap controller operates from 2.7v to 16.5v, so-8 or ssop-16 ltc4210 single channel, hot swap controller operates from 2.7v to 16.5v, active current limiting, sot23-6 ltc4211 single channel, hot swap controller operates from 2.5v to 16.5v, multifunction current control, msop-8 or msop-10 ltc4212 single channel, hot swap controller operates from 2.5v to 16.5v, power-up timeout, msop-10 ltc4214 negative voltage, hot swap controller operates from C 6v to C16v, msop-10 ltc4215 single channel, hot swap controller with i 2 c monitoring operates from 29v to 15v, 8-bit adc monitors current and voltage ltc4216 single channel, hot swap controller operates from 0v to 6v, msop-10 or 12-lead (4mm 3mm) dfn ltc4217 single channel, hot swap controller operates from 2.9v to 26.5v, integrated mosfet, tssop-20 or dfn-16 ltc4218 single channel, hot swap controller operates from 2.9v to 26.5v, 5% accurate current limit, ssop-16 or dfn-16 lt4220 positive and negative voltage, dual channel, hot swap controller operates from 2.7v to 16.5v, ssop-16 ltc4221 dual hot swap controller/sequencer operates from 1v to 13.5v, multifunction current control, ssop-16 ltc4224 dual channel, hot swap controller operates from 1v to 6v, compact, msop-10 or (3mm 2mm) dfn-10 figure 13. tca application supplying 12v payload power to two tca slots uv1 v dd1 ltc4222 gate1 intv cc adr2 adr1 nc adr0 config source1 uv2 v dd2 gate2 source2 ov1 ov2 alert scl sda on fb1 adin1 timer gpio1 en1 ss tca plug-in card 2 tca plug-in card 1 pwr good 1 pwr good 2 10 68nf 6m si7336adp 93.1k 12.1k 100k 4222 ta02a 0.1f 93.1k 2k 10.2k backplane gnd 12v 12v 12v adin2 fb2 gpio2 en2 0.1f 10 6m si7336adp 93.1k 12.1k 100k 0.1f 93.1k 2k 10.2k 12v 1f load 1 sense1 C sense2 C load 2

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